Digital to analogue converter description

ABSTRACT

A circuit for analogue to digital or digital to analogue conversion comprising at least 2n matched current sources ( 40 - 1, 40 - 2, 40 - n ), where n is the resolution required of the conversion. Preferably more than 2n current sources ( 40 - 1, 40 - 2, 40 - n ) are used. The order in which the sources ( 40 - 1, 40 - 2, 40 - n ) are used may be changed in different samples. The current sources ( 40 - 1, 40 - 2, 40 - n ) may be replaced by one bit switched capacitor converters or by inverters connected to one end of a set of resistors, the other ends of which are connected to the virtual ground for an operational amplifier or alternatively to each other and arranged to directly generate the output voltage. According to one embodiment of the invention there is provided a sigma-delta analogue to digital converter comprising the circuit of the first aspect. A method is also provided which can be done by controlling each source with a duty cycle of M/2n, where n is the required resolution of the converter and M is the input word, and controlling different sources with a time shift. This allows an equal contribution from all the elements in one sample period with reduced switching and low sensitivity for time jitter.

The present invention relates to a digital to analogue converter.

The performance of digital to analogue converters depends upon thedifferences between the circuit elements employed since not all elementsare common to the total signal flow. In particular, in practice, currentsources have tolerance differences and resistors are not all identical.

One conventional technique for improving performance is dynamic elementmatching (DEM).

One form of DEM technique used in some digital to analogue converters isknown as Data Weighted Averaging. A number of almost equal elements areinterchanged such that the mean deviation is zero. The actual deviationappears as a noise component that is shaped such that its contributionin the signalband is low, e.g. first or second order noise shaping. Theproblem with this application is that the noise under certain boundaryconditions can be mixed back into the signal band. An improvement wouldbe seen if all the elements were interchanged in one sample period, butthis can lead to very high switching frequencies and many switchingedges that are sensitive to time jitter.

For example, for n bit resolution and input word M, then conventionallym current switches are switched on and 32-m sources are off. All sourcesare given equal weighting over time.

The present invention aims to have an equal contribution from all theelements in one sample period with reduced switching and low sensitivityfor time jitter.

According to a second aspect of the present invention there is provideda circuit for signal conversion comprising at least 2^(n) matchedcurrent sources, where n is the resolution required of the conversion.

Preferably some more than 2^(n) current sources are used (with thenumber of clock phases accordingly adapted). The order in which thesources are used may be changed in different samples to reduce secondorder errors.

The converter is a digital to analogue converter that can be used in asigma-delta analogue to digital converter. The current sources may bereplaced by one bit switched capacitor converters or by invertersconnected to one end of a set of resistors, the other ends of which areconnected to the virtual ground of an operational amplifier oralternatively to each other and arranged to directly generate the outputvoltage.

According to one embodiment of the invention there is provided asigma-delta analogue to digital converter loop comprising the circuit ofthe first aspect.

According to one aspect of the invention there is provided a method fordigital to analogue conversion, the method comprising using 2^(n)current sources or one bit switched capacitor convertors and switchingon every source or convertor within each sampling period. This can bedone by controlling each source or convertor with a duty cycle ofM/2^(n), where n is the required resolution of the converter and M isthe input word, and controlling different sources with a time shift. Thetime shift is typically {fraction (1/32)} sampling period.

Preferably all clock pulses are made with different clock phases so thatthere is no correlation between the timing jitter of the pulses and thenoise.

In addition, the order in which the sources or convertors are used maybe changed for different samples.

According to a second aspect of the present invention there is provideda circuit for signal conversion comprising at least 2^(n) matchedcurrent sources, where n is the resolution required of the conversion.

Preferably some more than 2^(n) current sources are used (with thenumber of clock phases accordingly adapted). The order in which thesources are used may be changed in different samples to reduce secondorder errors.

The converter is a digital to analogue converter that can be used in asigma-delta analogue to digital converter. The current sources may bereplaced by one bit switched capacitor converters or by invertersconnected to one end of a set of resistors, the other ends of which areconnected to the virtual ground of an operational amplifier oralternatively to each other and arranged to directly generate the outputvoltage.

According to one embodiment of the invention there is provided asigma-delta analogue to digital converter loop comprising the circuit ofthe first aspect.

For a better understanding of the present invention, and to show how thesame may be carried into effect, reference will now be made, by way ofexample, to the accompanying drawings in which:

FIG. 1 is a timing diagram of two sample periods in a circuit inaccordance with the present invention.

FIG. 2 is a circuit diagram of one embodiment of part of a circuitaccording to the present invention.

FIG. 1 illustrates two sample periods each divided into 32 clock phases.Each clock phase therefore corresponds with a time interval that is{fraction (1/32)} of a sample period. Illustrated in FIG. 1 is a dutycycle of {fraction (7/32)}, i.e. each current source is switched on for{fraction (7/32)} of the total sample period. During each new clockphase, i.e. each {fraction (1/32)} of a sample period, one currentsource is switched on and another current source is switched off. Hence7 current sources are on all of the time and all current sources are onfor the same total time period because they all have the same dutycycle. Duty cycles that start at the end of a sample period continue inthe next sample period. For a constant output signal this is equivalentto a representation at the beginning of the sample period because of thecyclic character of the duty cycle generation.

Consider five current sources, i.e. n=5, then 2^(n)=32. Letting theinput word (truncated at 5 bits) be m then traditionally m sources wouldbe “on” and 32-m sources “off” and the arrangement would give allsources equal probability over time. The new invention controls eachsource to give it a duty cycle of m/32 so that every source comes “on”(and goes “off”) during each sampling period. The different sources arecontrolled with a time shift.

Additional current sources are preferable so as to minimise the effectsof edges. Duty cycles of 0% and of 100% do not have edges and thus theadditional current sources are used to introduce the same edges as forduty cycles between 0% and 100%. If extra sources are introduced, thesame number of extra phases must also be brought in.

Preferably all pulses are made with different clock phases so that thereis no correlation between the timing jitter of the different pulses.Hence the noise caused by the timing jitter ads only with the squareroot of the number of current sources.

A second order error arises if the time intervals are not exactly equalbecause of systematic differences in the timing of the different pulses.By changing the order in which the sources are used in different samplesthis error can be reduced.

The current sources may instead be one bit switched capacitor converters(in this case extra sources are not helpful in guaranteeing linearityfor all duty cycles.

The current sources can also be replaced by inverters driving resistorswith the other ends of the resistors connected to the virtual ground ofan operational amplifier or to each other and directly generating theoutput voltage.

By way of example consider an audio analogue to digital converter (ADC)with a sample rate fs=44.1 kHz, assuming an oversampling of 64 times forinterpolation and lowpass filtering so that the sample rate is64*fs=2.8224 MHz.

When high order noise shaping is used a one bit representation can giveenough resolution in the signal band but the level of the outbandquantisation noise is very high. A one bit DAC is therefore very noisesensitive, particularly if the converter is of the switched currenttype, due to the time jitter on the edges. A higher resolution is henceaimed at reducing the step size of the edges but the higher resolutioncan only be useful if the accuracy is in the same order of magnitude asthe dynamic range in the signal band. This also applies to ADCs.

To improve performance, for n bit resolution at least 2 to the power nmatched current sources are used.

For 5 bit resolution therefore 32 matched current sources are used. Thetraditional operation of such a DAC would be: m current sources on and32-m current sources off. All sources would be given equal probabilityover time.

According to this invention every source is on within each samplingperiod by controlling each source with a duty cycle of m/32 andintroducing a time shift.

A circuit according to this invention is an improvement over an R-2Rnetwork since no new inaccuracies are introduced into the new circuitry,timing accuracy is not critical and Inter Symbol Interference (ISI) iszero.

The new circuit operates as a so-called “thermometer” DAC as distinctfrom a binary weighted DAC formed by R-2R networks.

FIG. 2 illustrates part of a circuit incorporating the teaching of thisinvention. This circuit is adapted for 5 bit resolution and thus has 32DAC current sources of which three are shown in the FIG. 40-1, 40-2,40-29. The current sources are supplied from the outputs of shiftregister stage 50-1, 50-2, 50-29 respectively.

The shift register input is supplied via gating logic 60, and a clockedflip-flop 70 by the 5 bit input data indicated at 80. Each data bit iscombined with the inverted outputs an (most significant bit), Bn, Cn,Dn, En (least significant bit) of a binary counter 95, and issubsequently combined in AND gate 90. The resulting signal supplies thereset input R of flip-flop 70.

The set input 5 of flip-flop 70 is supplied from word clock 86. Clock 86also feeds the binary counter 95 via a phase detector 87 a loop filter88 and a VCO 89 which feeds the least significant bit E of the counter95. The most significant bit of A of the counter 95 in turn feeds thephase detector 87 in a loop.

1. A method for digital to analogue conversion, the method comprisingusing 2^(n) current sources (40-1, 40-2′″, 40-n) and, within eachsampling period switching on and off every source.
 2. A method accordingto claim 1 comprising controlling each source (40-1, 40-2′″, 40-n) witha duty cycle of M/2^(n), where n is the required resolution of theconverter and M is the input word, and controlling different sources(40-1, 40-2, 40-n) with a time shift.
 3. A method according to claim 1wherein all clock pulses are made with different time equidistant clockphases.
 4. A method according to claim 1 wherein the order in which thesources (40-1, 40-2, 40-n) are made is changed for different samples. 5.A method according to claim 1 wherein the order in which the sources(40-1, 40-2, 40-n) are used is changed in different sampling periods. 6.A method according to claim 1 wherein each of the current sources (40-1,40-2′″, 40-n) comprise a one bit switched capacitor converter.
 7. Acircuit for signal conversion comprising at least 2^(n) matched currentsources (40-1, 40-2′″, 40-n) where n is the resolution required of theconversion.
 8. A circuit according to claim 7 comprising more than 2^(n)current sources (40-1, 40-2, 40-n).
 9. A circuit according to claim 7comprising a digital to analogue converter.
 10. A circuit according toclaim 7 comprising an analogue to digital converter.
 11. A circuitaccording to claim 7 wherein the current sources comprise one bit itchedcapacitor converters.
 12. A circuit according to claim 7 wherein thecurrent sources (40-1, 40-2′″ 40-n) comprise inverters connected to oneend of a set of resistors, the other ends of which are connected to thevirtual ground for an operational amplifier or to each other andarranged to directly generate an output voltage.
 13. A sigma-deltaanalogue to digital converter comprising the circuit of claim 7.